An asynchronous successive approximation register analog-to-digital converter SAR ADC with small size and low power has been more required according as usage of a low power application such as a mobile device has been increased.
The asynchronous SAR ADC has rapid conversion velocity by generating desired number of internal clocks corresponding to one external clock. However, the asynchronous SAR ADC has a demerit in that a delay time by a delay block for assuring stability time of a capacitor digital-to-analog converter CDAC changes passively according to variation of a corner and a temperature. That is, in the asynchronous SAR ADC, the delay time generated by the delay block is passively changed according to the variation of the corner and the temperature, and so stability error of the capacitor DAC in the SAR ADC may occur and every bit may not be converted in one external clock.